1. Field of the Invention
The invention relates to the field of integrated circuits, and particularly to electrically programmable read only memories.
2. Prior Art
Electrically programmable read only memory integrated circuits are well known to the art. See, for example, U.S. Pat. Nos. 3,660,819 (1972), 3,744,036 (1973), and 3,755,721 (1973).
A widely-used structure for this type of memory is illustrated by the ultraviolet erasable 2048.times.8 PROM known in the electronics industry as the 2716. The 2716 contains 16,384 floating-gate MOS transistors arranged in a matrix of rows and columns. Each floating gate transistor actually has two gates, the floating gate and a second gate which is connected to one of a plurality of row-select lines. The floating gate is insulatively disposed between the second gate and the channel of the transistor. The storage of a binary 0 or 1 is determined by the "apparent threshold voltage" of the transistor, the apparent threshold voltage being the value of voltage required to be applied to the second gate so as to cause a conductive channel to be established between the drain and source of the transistor. When no excess electrical charge is stored on the floating gate, the apparent threshold voltage of a typical transistor is +2V, a value which allows the channel to become quite conductive when +5V is applied to the second gate via the row-select line. But if sufficient excess electrical charge is stored on the floating gate, the apparent threshold voltage of the transistor increases to a value greater than +5V, e.g. +8V. With such a high apparent threshold voltage, the channel will not become conductive when +5V is applied to the second gate. To read an addressed bit, circuitry connected to the drain of the addressed transistor is utilized to detect whether or not the transistor is conductive. Thus, the storage of a 0 or a 1 is dependent upon the presence of or lack of excess electrical charge on the floating gate, the presence of charge resulting in the storage of a 0 and the lack of charge resulting in the storage of a 1.
Ideally, charge "programmed" onto a floating gate will remain trapped on that gate until "erased" by exposure of the transistor to ultraviolet light. It is also desirable that sufficient charge be trapped so as to create a margin of safety between the apparent threshold voltage and the row-selection voltage when reading. The programming time required to insure that sufficient charge is trapped may vary from one storage transistor to another. Nevertheless, manufacturers of floating-gate PROMs typically recommend that each 0 bit be programmed for at least 45 milliseconds. But this time is much longer than is necessary for many devices. The present invention provides a practical means for readily determining the apparent threshold voltage of each of the programmable transistors within a PROM, allowing a faster method of programming to be utilized. This faster method of programming is described in detail in the description of the preferred embodiments.
Also, the act of programming a 0 into a selected transistor often causes previously programmed transistors in the same row to lose some percentage of their stored charge, thus lowering the apparent threshold voltage of previously programmed transistors. This deleterious effect is called "deprogramming." If too much charge is lost, the apparent threshold voltage becomes too marginal for reliable operation. To alleviate this problem, manufactures of floating gate PROMs typically specify that each 0 bit be programmed for no longer than 55 milliseconds. In addition, some transistors within a PROM may exhibit a marginal threshold voltage for reasons other than the deprogramming effect. In the prior art, there is no convenient means to test for marginal programming; hence, there is no practical means to insure reliable operation. Prior art testing typically consists only of programming various bit patterns into the PROM and operating the PROM at worst case operating voltages.
However, the present invention provides a means for simultaneously subjecting all programmable transistors within a PROM to a deprogramming stress, thus reducing the number of bit patterns which must be programmed into the PROM for testing. The present invention further provides a means for readily and accurately determining the margin of safety of threshold voltage of each programmable transistor within the PROM. Consequently, a more reliable operation is accomplished.